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specifications of any and all sanyo semiconductor co.,ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' s products or equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment. the products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for new introduction or other application different from current conditions on the usage of automotive device, communication device, office equipment, industrial equipment etc. , please consult with us about usage conditi on (temperature, operation time etc.) prior to the intended use. if there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. 42512 sy 20111214-s00006 no.a2010-1/20 LC08101CT overview the LC08101CT is a shaft slide actuator driver ic. features the shaft slide actuator can be driven simply by i 2 c communication. constant current control is exercised for the output of the supply to suppress the fluctuation in the coil current due to the temperature fluctuations. ? the drive conditions can be set externally using serial input through the i 2 c interface. the kick-pulse width and brake-pulse width are set using the clock count. ? enin input that controls the startup/stop of the ic. ? the time for which the actuator is driven is determined with the drive frequency setting based on i 2 c communication. ? provides a busy signal output during periods when the actuator is being driven by out pin output so that applications can be aware of the actuator operating/stopped state. ? built-in oscillator circuit (1 mhz typical). capable of switching to an external clock. ? separate drive waveforms can be set in steps, i.e., when the actuator is activat ed, stopped and subjected to braking. ? built-in thermal protection function, reduced voltage detecti on/protection circuits, and register power-on reset function specifications absolute maximum ratings at ta = 25 c, sgnd = pgnd = 0v parameter symbol conditions ratings unit supply voltage v cc max -0.5 to 4.0 v output current i o max 300 ma input signal voltage v in max scl/sda/clk/wp -0.5 to v cc +0.5 v allowable power dissipation pd max *mounted on a specified board. 650 mw operating temperature topr -30 to +85 c storage temperature tstg -55 to +150 c *: when mounted on the specif ied printed circuit board (50mm 50mm 1.6mm), glass epoxy board caution 1) absolute maximum ratings represent the va lue which cannot be exceeded for any length of time. caution 2) even when the device is used within the range of absolu te maximum ratings, as a result of continuous usage under hig h temperature, high current, high voltage, or drastic temperature change, the reliability of the ic may be degraded. please contact us for the further details. bi-cmos ic shaft slide actuator driver ic orderin g numbe r : ena2010
LC08101CT no.a2010-2/20 allowable operating conditions at ta = 25 c, sgnd = pgnd = 0v parameter symbol conditions ratings unit supply voltage v cc 2.2 to 3.6 v input signal voltage v in -0.3 to v cc v corresponding clk input frequency fclk to 60 mhz maximum operating frequency ct max set stp count 512 times electrical characteristics at ta = 25c, v cc = 2.8v, sgnd = pgnd = 0v, unless otherwise specified. parameter symbol conditions ratings unit min typ max standby mode current drain i cc 0 clk/scl/sda=0v, when enin=0 1.0 a operating mode current drain for driber area i cc 1 internal oscillator movement scl/sda=0, when enin=1 0.65 1.0 ma high-level input voltage v ih 2.2v v cc 3.3v scl, sda 1.4 v cc +0.3 v low-level input voltage v il 2.2v v cc 3.3v scl, sda -0.3 0.3 v clk pin high-level input voltage v ih 2 clk 0.45 v cc v cc +0.3 v clk pin low-level input voltage v il 2 clk -0.3 0.2 v cc v internal oscillator dispatch frequency fclk it is calculated by an out put wave pattern 0.80 0.95 1.20 mhz output constant current i o c1 i out register d3 to d0 = 1010 95 105 115 ma i o c2 i out register d3 to d0 = 0000 190 210 230 ma reduced voltage protection detection voltage vres v cc voltage 1.8 2.0 2.2 v output block upper-side on resistance ronp i include a current current sense resistor 1.35 1.545 output block lower-side on resistance ronn 0.4 0.55 turn on time tplh with no load *1 0.1 0.25 s turn off time tphl with no load *1 0.03 0.1 s *1 : rising time from 10 to 90% and falling time from 90 to 10% are specified with regard to the out pin voltage. package dimensions unit : mm (typ) 3423 pd max - ta 0 0.34 1.0 0.65 0.4 0.6 0.2 ? 30 90 30 60 0 120 0.8 specified board : 50 50 1.6mm 3 glass epoxy allowable power dissipation, pd max - w ambient temperature, ta - c sanyo : wlp8(1.57x0.77) top view side view side view bottom view 0.22 laser marked index 1 2 3 4 0.33 max 0.08 (0.19) 0.77 1.57 a b 0.185 0.4 0.185 0.4
LC08101CT no.a2010-3/20 pin assignment a1:clk b1:clk a2:sda b2:sgnd a3:out1 b3:v cc a4:pgnd b4:out2 clk scl sda sgnd v cc out1 out2 4 3 2 1 clk scl sda sgnd v cc out1 out2 4 3 2 1 b a b a top view ball side view 0.4 0.4 0.77 1.57 pgnd pgnd
LC08101CT no.a2010-4/20 block diagram sgnd clk scl sda out2 out1 v cc pgnd constant current amp constant current dac thermal protection circuit ssa drive waveform creation register output control i 2 c interface clk select start-up block osc busy signal
LC08101CT no.a2010-5/20 serial bus communication specifications i 2 c serial transfer timing conditions standard mode parameter symbol conditions min typ max unit scl clock frequency fscl scl clock frequency 0 - 100 khz data setup time ts1 setup time of scl with respect to the falling edge of sda 4.7 - - s ts2 setup time of sda with respect to the rising edge of scl 250 - - ns ts3 setup time of scl with respect to the rising edge of sda 4.0 - - s data hold time th1 hold time of scl with respect to the rising edge of sda 4.0 - - s th2 hold time of sda with respect to the falling edge of scl 0.06 - - s pulse width twl scl low period pulse width 4.7 - - s twh scl high period pulse width 4.0 - - s input waveform conditions ton scl/ sda (input) rising time - - 1000 ns tof scl/ sda (input) falling time - - 300 ns bus free time tbuf interval between stop condition and start condition 4.7 - - s high speed mode parameter symbol conditions min typ max unit scl clock frequency fscl scl clock frequency 0 - 400 khz data setup time ts1 setup time of scl with respect to the falling edge of sda 0.6 - - s ts2 setup time of sda with respect to the rising edge of scl 100 - - ns ts3 setup time of scl with respect to the rising edge of sda 0.6 - - s data hold time th1 hold time of scl with respect to the rising edge of sda 0.6 - - s th2 hold time of sda with respect to the falling edge of scl 0.06 - - s pulse width twl scl low period pulse width 1.3 - - s twh scl high period pulse width 0.6 - - s input waveform conditions ton scl/ sda (input) rising time - - 300 ns tof scl/ sda (input) falling time - - 300 ns bus free time tbuf interval between stop condition and start condition 1.3 - - s th1 ton ts2 th2 twh twl sda scl start condition input waveform condition stop condition ts1 ts3 th1 resend start condition tbuf tof
LC08101CT no.a2010-6/20 i 2 c bus transfer method start and stop conditions the i 2 c bus requires that the state of sda be preserved while scl is high as shown in the timing diagram below during a data transfer operation. when data is not being transferred, both scl and sda are in the high state. the start condition is generated and access is started when sda is changed from high to low while scl and sda are high. conversely, the stop condition is generated and access is e nded when sda is changed from low to high while scl is high. data transfer and acknowledgement response after the start condition is generated, data is transferred on e byte (8 bits) at a time. any number of data bytes can be transferred consecutively. an ack signal is sent to the sending side from the receiving side every time 8 bits of data are transferred. the transmission of an ack signal is perform ed by setting the receiving side sda to low after sda at the sending side is released immediately after the clock pulse of sc l bit 8 in the data transferred has fallen low. after the receiving side has sent the ack signal, if the next byte transfer operation is to receive only the byte, the receiving side releases sda on the fa lling edge of the 9th clock of scl. there are no ce signals in the i 2 c bus ; instead, a 7-bit slave address is assigned to each device, and the first byte of the transfer data is allocated to the 7- bit slave address and to the command (r /w) which specifies the direction of subsequent data transfer. the read function of the LC08101CT driver area provi des only the functionality to test the busy state. 7-bit address data is tr ansferred sequentially starting at the msb and th e second and subsequent bytes are written if the state of the 8th bit is low and read if the state is high. in the LC08101CT driver area, the slave ad dress is stipulated to be ?1110010.? write mode timing ts2 th2 scl sda th1 th3 scl sda start condition stop condition m s b l s b a c k l s b a c k m s b m s b l s b a c k w x scl sda start stop xxxxxx0 00 1 1 000 0 000 0 000 1 slave address register address data
LC08101CT no.a2010-7/20 read mode timing data transfer write format the slave address and write command must be allocated to the first byte and the re gister address in the serial map must be designated in the second byte. for the third byte, data transfer is carried out to the addr ess designated by the register address which is written in the second byte. subsequently, if data continues, the register address value is automatically incremented for the fourth and subsequent bytes. thus, continuous data transfer starting at th e designated address is made possible. after the register address reaches 1fh, the transf er address for the next byte is set to 00h. data write example s 1 1 1 0 0 1 0 0 a 0 0 0 0 0 0 1 0a data 1 a slave address register address set to 02h write data to address 02h r/w = 0 written data 2 a data 3 a data 4 a p write data to address 03h write data to address 04h write data to address 05h s start condition p stop condition a a ack signal master side transmission slave side transmission data read example s 1 1 1 0 0 1 0 1 a data a p slave address read data r/w = 1 read notify end of read by not sending out ack s start condition p stop condition a a ack signal master side transmission slave side transmission l s b a c k m s b m s b l s b a c k r stop x scl sda start xxxxxx1 10 0 0 000 0 0 slave address data
LC08101CT no.a2010-8/20 driver area serial map register address data a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 m/i drvpulse[6:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 enin cksel[1:0] inclk[1:0] bron 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 rst[7:0] 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 gtas[7:0] 3 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 stp[7:0] 4 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 test[1:0] sw1 sw2 iout[3:0] 5 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 tbrake[7:0] 6 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 nrpulse1[5:0] 7 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 nrp-a[5:0] 8 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 nrp-b[5:0] 9 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 nrp-c[5:0] 10 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 nrp-d[5:0] 11 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 nrpulse2[5:0] 12 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 nrp-e[5:0] 13 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 nrp-f[5:0] 14 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 nrp-g[5:0] 15 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 nrp-h[5:0] 16 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 nrpulse3[5:0] 17 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 nrp-i[5:0] 18 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 nrp-j[5:0] 19 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 nrp-k[5:0] 20 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 nrp-l[5:0] 21 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 nrpulse4[5:0] 22 0 0 0 0 0 0 0 0 register address data upper : register name lower : default value continued on next page.
LC08101CT no.a2010-9/20 continued from preceding page. register address data a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 1 0 1 1 1 nrp-m[5:0] 23 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 nrp-n[5:0] 24 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 nrp-o[5:0] 25 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 nrp-p[5:0] 26 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 nr1gtas[7:0] 27 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 nr2gtas[7:0] 28 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 nr3gtas[7:0] 29 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 nr4gtas[7:0] 30 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 nr5gtas[7:0] 31 0 0 0 0 0 0 0 0 read mode only register busy 32 0 0 0 0 0 0 0 0 register address data upper : register name lower : default value nr pulse output rise-time operation if, as an example, the nrpulse1 setting is set to 15, the nr p-a setting is set to 3, the nrp-b setting is set to 6, the nrp-c setting is set to 9 and the nrp-d setting is set to 12, then after the nr1 waveform is output for three periods, the nr2 waveform for three periods, the nr3 waveform for three periods, the nr4 waveform for three periods and the nr5 waveform for three periods, the standard waveform is output for a period equivalent to the stp x drvpulse period. when the nrpulse setting is set to 0, the same output as the normal drvpulse input without the nr pulses is performed. when the same value has been set for nrp-a and nrp-b, the nr2 waveform is not output, and the nr3 waveform is output after the nr1 waveform. nr2 nr3 nr4 nr5 nrp-b nrp-c nrp-d drvpulse communication input nrpulse1 setting frequency busy output out output nr1 wave standard wave nrp-a setting frequency
LC08101CT no.a2010-10/20 fall-time operation during the fall-time operation, the waveforms are output in sequence from the nr5 waveform to the nr1 waveform. the method used to set the switching timing is the same as for the rise-time operation. nr drive waveform settings the settings are the same as for the normal drive waveform. the same parameter as for the normal waveform is used for rst, and for gtas the drive waveform is generated using the setting values for the nr waveforms. nr pulse output when the brake is set when the brake output has been set, a pulse equivalent to the tbrake frequency is output as the brake pulse in the reverse direction after the standard waveform has been output . if the nr settings are to be established, nr pulses can be set separately for the rise and fall of the standard waveform and the rise and fall of the brake waveform. when the brake setting is not to be established (when the bron register is set to 0), the pulse is not output in the reverse direction so it is not output even when values have been set for nrpulse3 and nrpulse4. nr2 nr3 nr4 nr5 nrp-e nrp-f nrp-g nr1 nrp-h nrpulse2 setting frequency busy output out output standard wave rst = number of clock pulses in period minus 1 gtas = ta + 1 waveform start reference point rises here after two clock pulses from reference. ta - 1 + 2 = ta + 1 since the waveforms start after two clock pulses. nr1 nr2 nr3 nr4 nr5 nr1 nr2 nr3 nr4 nr5 nr1 nr2 nr3 nr4 nr5 nr1 nr2 nr3 nr4 nr5 busy output out output standard wave drvpulse communication input nrpulse1 setting frequency nrpulse2 setting frequency nrpulse3 setting frequency nrpulse4 setting frequency brake wave forward-direction operation reverse-direction operation
LC08101CT no.a2010-11/20 serial mode settings 0 0 0 0 0 0 0 0 0 d7 d6 d5 d4 d3 d2 d1 d0 d0 to d6: drvpulse [6 : 0] operation count setting register. specify a number from 0 to 127. the number of cyclic operations determined by are performed. additional data can be input and data is added up to the equivalent of total of 512 pulses. however, if the enin register is set to 0, the drvpulse input is not accep ted because the drvpulse counter is in the reset state. since the output operation is carried out at the time the drvpulse input is recognized, the generation of the out signal is started at the time an ack signal is generated after the execution of the instruction at address 00h according to the valu e of the waveform setup register established at that time. d7 m/i operation direction switching 0 *defaul t infinity distance direction 1 macro macro direction operation direction switching register the operation count setting register is reset when the regi ster is switched. to stop the operation of the unit, switch the m/i register and set drvpulse to 0 for input. 1 0 0 0 0 0 0 0 1 0 0 d5 d4 d3 d2 d1 d0 d0: the register who selects whether you output brakes pulse after the movement end by the drvpulse input automatically. d0 bron initialization to be performed/not to be performed setting 0 no brake *defaul t 1 on brake d1, d2: the register who sets frequency of the oscilla tory frequency when you operate an internal oscillator circuit. d2 d1 inclk n umber of initialization sequence swing bac k 0 0 oscillator stop *defaul t 0 1 1.02mhz 1 0 1mhz 1 1 0.98mhz d3, d4: register (when i use an internal oscillation invalidity) who sets the ratio to do a share lap when i count it in a clock pulse input into clk pin or the ic inside as basic time. d4 d3 cksel input clock division ratio switching 0 0 1/4 *defaul t 1/4 0 1 1/2 1/2 1 0 1 1 (no frequency division) 1 1 1 1 (no frequency division) d5 : enin enin register is a regist er setting start, the stop of the ic. only as for the state of enin=1, the output of the ic operates. it becomes a wait mode at the time of enin=0. 2 0 0 0 0 0 0 1 0 d7 d6 d5 d4 d3 d2 d1 d0 rst7 to rst0 : specifies the number of clocks per period (0 to 255). default = 0 3 0 0 0 0 0 0 1 1 d7 d6 d5 d4 d3 d2 d1 d0 gtas7 to gtas0 : sets the gate_a pulse set value (0 to 255). default = 0
LC08101CT no.a2010-12/20 4 0 0 0 0 0 1 0 0 d7 d6 d5 d4 d3 d2 d1 d0 stp7 to stp0 : output pulse step number for the drive input (1 to 256). default = 1 +1 is the quantity that i did, and the set range is treated in data level. when i input at 8 bits (0 to 255), it is treated in stp setting period of 1 to 256. 5 0 0 0 0 0 1 0 1 d7 d6 d5 0 d3 d2 d1 d0 d0 to d3: iout3 to iout0 output constant current level setting (0 to 15). default = 210ma typical d3 d2 d1 d0 iout3 to iout0 ou tput current setting(typical) 0 0 0 0 0 210ma 0 0 0 1 1 199ma 0 0 1 0 2 189ma 0 0 1 1 3 178ma 0 1 0 0 4 168ma 0 1 0 1 5 157ma 0 1 1 0 6 147ma 0 1 1 1 7 136ma 1 0 0 0 8 126ma 1 0 0 1 9 115ma 1 0 1 0 10 105ma 1 0 1 1 11 94ma 1 1 0 0 12 84ma 1 1 0 1 13 73ma 1 1 1 0 14 63ma 1 1 1 1 15 52ma d4, d5: sw1, sw2 it is a current value adjustment bit of the constant current output. please usually use it in 00 setting at the time of use. d6, d7: test1, test0 i use it with the test mode of the driver ic. please usually use it in 00 setting at the time of use. 6 0 0 0 0 0 1 1 0 d7 d6 d5 d4 d3 d2 d1 d0 d0 to d7 : tbrake0 to tbrake7 brakes pu lse frequency setting (1 to 256). default = 1 the setting value range is handled as the data value plus 1. if, when the bron register is set to 1, a drive co mmand based on drvpulse is input, the brake pulse is output in the reverse direction after the normal operation has ended. the reverse-direction operation for the number of periods set by tbrake (the same drive waveform as when m/i is switched) is performed. 7 0 0 0 0 0 1 1 1 0 0 d5 d4 d3 d2 d1 d0 nrpul15 to nrpul10 (0 to 63). default = 0 the total output frequency is set for the drive waveforms from nr1 to nr5 during the rise when a multiple number of drive waveforms are output continuously during actuator operation. if 0 has been set, the nr drive waveforms are not output for the rise, and the normal operation is performed. 8 0 0 0 0 1 0 0 0 0 0 d5 d4 d3 d2 d1 d0 nrp-a5 to nrp-a0 (0 to 63). default = 0 this register sets the timing of the first switching for the rise-time nr drive waveforms. the number of periods for which the nr1 waveform is to be output is set. 9 0 0 0 0 1 0 0 1 0 0 d5 d4 d3 d2 d1 d0 nrp-b5 to nrp-b0 (0 to 63). default = 0 this register sets the timing of the second switching for the rise-time nr drive waveforms. it outputs the
LC08101CT no.a2010-13/20 nr2 waveform for the number of periods that is the difference between nrp-a and nrp-b.
LC08101CT no.a2010-14/20 10 0 0 0 0 1 0 1 0 0 0 d5 d4 d3 d2 d1 d0 nrp-c5 to nrp-c0 (0 to 63). default = 0 this register sets the timing of the third switching fo r the rise-time nr drive waveforms. it outputs the nr3 waveform for the number of periods that is the difference between nrp-b and nrp-c. 11 0 0 0 0 1 0 1 1 0 0 d5 d4 d3 d2 d1 d0 nrp-d5 to nrp-d0 (0 to 63). default = 0 this register sets the timing of the fourth switching for the rise-time nr drive waveforms. the nr4 waveform is output for the number of period s that is the difference between nrp-c and nrp-d , and the nr5 waveform is output for the number of periods that is the difference between nrp-d and nrpul1. when setting the rise-time nr drive waveforms, set values which, in principle, satisfy the following relationship: nrp-a nrp-b nrp-c nrp-d (if this relationship is not satisfied, unintended drive waveforms may be output, but the ic will not be broken or damaged as a result.) 12 0 0 0 0 1 1 0 0 0 0 d5 d4 d3 d2 d1 d0 nrpul25 to nrpul20 (0 to 63). default = 0 the total output frequency is set for the drive waveforms from nr1 to nr5 during the fall when a multiple number of drive waveforms are output continuously during actuator operation. if 0 has been set, the nr drive waveforms are not output for the rise, and the stops. 13 0 0 0 0 1 1 0 1 0 0 d5 d4 d3 d2 d1 d0 nrp-e5 to nrp-e0 (0 to 63). default = 0 this register sets the timing of the first switching for the fall-time nr drive waveforms. the number of periods for which the nr5 waveform is to be output is set. 14 0 0 0 0 1 1 1 0 0 0 d5 d4 d3 d2 d1 d0 nrp-f5 to nrp-f0 (0 to 63). default = 0 this register sets the timing of the second switching for the fall-time nr drive waveforms. it outputs the nr4 waveform for the number of periods that is the difference between nrp-e and nrp-f. 15 0 0 0 0 1 1 1 1 0 0 d5 d4 d3 d2 d1 d0 nrp-g5 to nrp-g0 (0 to 63). default = 0 this register sets the timing of the third switching fo r the fall-time nr drive waveforms. it outputs the nr3 waveform for the number of periods that is the difference between nrp-f and nrp-g. 16 0 0 0 1 0 0 0 0 0 0 d5 d4 d3 d2 d1 d0 nrp-h5 to nrp-h0 (0 to 63). default = 0 this register sets the timing of the fourth switching for the fall-time nr drive waveforms. the nr2 waveform is output for the number of periods that is the difference between nrp-g and nrp-h , and the nr1 waveform is output for the number of periods that is the difference between nrp-h and nrpul2. when setting the fall-time nr drive waveforms, set values which, in principle, satisfy the following relationship: nrp-e nrp-f nrp-g nrp-h (if this relationship is not satisfied, unintended drive waveforms may be output, but the ic will not be broken or damaged as a result.)
LC08101CT no.a2010-15/20 17 0 0 0 1 0 0 0 1 0 0 d5 d4 d3 d2 d1 d0 nrpul35 to nrpul30 (0 to 63). default = 0 the total output frequency is set for the drive waveforms from nr1 to nr5 during the rise when a multiple number of drive waveforms are output continuously during actuator operation. if 0 has been set, the nr drive waveforms are not output for the rise, and the start brake output. 18 0 0 0 1 0 0 1 0 0 0 d5 d4 d3 d2 d1 d0 nrp-i5 to nrp-i0 (0 to 63). default = 0 this register sets the timing of the first switching for the rise-time nr drive waveforms. the number of periods for which the nr1 waveform is to be output is set. 19 0 0 0 1 0 0 1 1 0 0 d5 d4 d3 d2 d1 d0 nrp-j5 to nrp-j0 (0 to 63). default = 0 this register sets the timing of the second switching for the rise-time nr drive waveforms. it outputs the nr2 waveform for the number of periods that is the difference between nrp-i and nrp-j. 20 0 0 0 1 0 1 0 0 0 0 d5 d4 d3 d2 d1 d0 nrp-k5 to nrp-k0 (0 to 63). default = 0 this register sets the timing of the third switching fo r the rise-time nr drive waveforms. it outputs the nr3 waveform for the number of periods that is the difference between nrp-j and nrp-k. 21 0 0 0 1 0 1 0 1 0 0 d5 d4 d3 d2 d1 d0 nrp-l5 to nrp-l0 (0 to 63). default = 0 this register sets the timing of the fourth switching for the rise-time nr drive waveforms. the nr4 waveform is output for the number of periods that is the difference between nrp-k and nrp-l , and the nr5 waveform is output for the number of periods that is the difference between nrp-l and nrpul3. when setting the rise-time nr drive waveforms, set values which, in principle, satisfy the following relationship: nrp-i nrp-j nrp-k nrp-l (if this relationship is not satisfied, unintended drive waveforms may be output, but the ic will not be broken or damaged as a result.) 22 0 0 0 1 0 1 1 0 0 0 d5 d4 d3 d2 d1 d0 nrpul45 to nrpul40 (0 to 63). default = 0 the total output frequency is set for the drive waveforms from nr1 to nr5 during the fall when a multiple number of drive waveforms are output continuously during actuator operation. if 0 has been set, the nr drive waveforms are not output for the rise, and the stops. 23 0 0 0 1 0 1 1 1 0 0 d5 d4 d3 d2 d1 d0 nrp-m5 to nrp-m0 (0 to 63). default = 0 this register sets the timing of the first switching for the fall-time nr drive waveforms. the number of periods for which the nr5 waveform is to be output is set. 24 0 0 0 1 1 0 0 0 0 0 d5 d4 d3 d2 d1 d0 nrp-n5 to nrp-n0 (0 to 63). default = 0 this register sets the timing of the second switching for the fall-time nr drive waveforms. it outputs the nr4 waveform for the number of periods that is the difference between nrp-m and nrp-n.
LC08101CT no.a2010-16/20 25 0 0 0 1 1 0 0 1 0 0 d5 d4 d3 d2 d1 d0 nrp-o5 to nrp-o0 (0 to 63). default = 0 this register sets the timing of the third switching fo r the fall-time nr drive waveforms. it outputs the nr3 waveform for the number of periods that is the difference between nrp-n and nrp-o. 26 0 0 0 1 1 0 1 0 0 0 d5 d4 d3 d2 d1 d0 nrp-p5 to nrp-p0 (0 to 63). default = 0 this register sets the timing of the fourth switching for the fall-time nr drive waveforms. the nr2 waveform is output for the number of periods that is the difference between nrp-o and nrp-p , and the nr1 waveform is output for the number of periods that is the difference between nrp-p and nrpul4. when setting the fall-time nr drive waveforms, set values which, in principle, satisfy the following relationship: nrp-m nrp-n nrp-o nrp-p (if this relationship is not satisfied, unintended drive waveforms may be output, but the ic will not be broken or damaged as a result.) 27 0 0 0 1 1 0 1 1 d7 d6 d5 d4 d3 d2 d1 d0 nr1gtas7 to nr1gtas0 (0 to 255). default = 0 gate_a pulse set value for nr1 waveform 28 0 0 0 1 1 1 0 0 d7 d6 d5 d4 d3 d2 d1 d0 nr2gtas7 to nr2gtas0 (0 to 255). default = 0 gate_a pulse set value for nr2 waveform 29 0 0 0 1 1 1 0 1 d7 d6 d5 d4 d3 d2 d1 d0 nr3gtas7 to nr3gtas0 (0 to 255). default = 0 gate_a pulse set value for nr3 waveform 30 0 0 0 1 1 1 1 0 d7 d6 d5 d4 d3 d2 d1 d0 nr4gtas7 to nr4gtas0 (0 to 255). default = 0 gate_a pulse set value for nr4 waveform 31 0 0 0 1 1 1 1 1 d7 d6 d5 d4 d3 d2 d1 d0 nr5gtas7 to nr5gtas0 (0 to 255). default = 0 gate_a pulse set value for nr5 waveform 32 no register address d7 0 0 0 0 0 0 0 this is a read-only register line. d7: busy register ?1? is output during output operations; ?0? is output when the output has stopped.
LC08101CT no.a2010-17/20 functional description 1 period : one period of out waveform operation is equivalent to one output operation. clk input : the pin for the external clk input that provides the reference time for generating drive waveforms. the frequency divi sion ratio for i 2 c communication can be selected from 1/4, 1/2, and 1/1. drive waveforms are generated by counting this frequency-divided clk pulses as the basic count unit. the LC08101CT supports frequency from 10mhz to 60mhz depending on the frequency division ratio and counter settings. register setup sequence : (1) apply v cc . (2) set register addresses 0x01 to 0x1f (set the waveform and drive conditions). (3) set the enin register to 1 (invoke initialization proced ures if initialization is enabled or start up the ic). (4) set up m/i and drvpulse to start the af operation (actuator op eration instruction). i 2 c communication during output operation : i 2 c communication with all the registers is possible even when the ic is in operation (out processing or busy is held high). however, if the drive waveform settings have been change d while the actuator is operating, for example, there is a possibility that unintended waveforms are output. f = 1 period ta
LC08101CT no.a2010-18/20 actuator drive waveform settings : configuration of piezoelectric actuator drive waveform drive parameter settings the drive waveforms are set using four parameters: rst, gtas, gtbr and gtbs. rst : parameter determines the period, and sets the reference clock pulse count minus 1. gtas : parameter determines the time taken for the gate signal a to the falling edge from the reference point. since the signal raises after two clock pulses from the reference, the ta reference clock cycle count plus 1 is set. [example of settings] when setting reference clock to 10mhz, period to 13 s, ta to 2.0 s since the reference clock time is 0.1 s : the period is 130 clks. specify 129 (rst value of 130 -1). ta is 20 clks. specify 21 (gtas value of 20 + 1). f = 1 period ta rst = number of clock pulses in period minus 1 gtas = ta + 1 waveform start reference point rises here after two clock pulses from reference. ta - 1 + 2 = ta + 1 since the waveforms start after two clock pulses. since the counter starts from zero, a value minus 1 is set.
LC08101CT no.a2010-19/20 timing charts enlarged view of the sequence of output signals drvpulse input sequence (rst setting + 1) number of clock pulses (rst setting + 1) number of clock pulses (gtas setting - 1) number of clock pulses (gtas setting - 1) number of clock pulses (gtas setting - 1) number of clock pulses (gtas setting - 1) number of clock pulses out1 operation toward infinity operation toward macro out2 out1 out2 out1 out2 m/i register state enin register drvpulse setting busy register operation stops when enin input is low. macro direction logic selection infinity direction logic selection serial communication operation instruction completed 00000000_00000010 (operation 2 times toward infinity) serial communication operation instruction completed 00000000_10000010 (operation 2 times toward macro) equivalent to 2 pulses = stp setting period operation for 2 times 1 period operation toward infinity (stp setting period 2 times) operation toward macro serial communication operation starts on completion of drvpulse input. return to high when en is set to low even before the completion of the operation. busy output high, only during operation period on out2 out1 forward off on off out1 out2 forward forward brake output-tr on/off truth table 1 period on out2 out1 reverse output mode off on off on out2 out1 braking off on off
LC08101CT ps no.a2010-20/20 this catalog provides information as of april, 2012. specifications and information herein are subject to change without notice. sanyo semiconductor co.,ltd. assumes no responsib ility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-quality high-reliab ility pr oducts, however, any and all semiconductor products fail or malfunction with some probab ility. it is possible that these pr obab ilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause dam age to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equip ment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor co.,ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd.

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